LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 144

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-56
31
x
x
x
x
x
x
x
Registers: 0x1C–0x1F (0x9C–0x9F)
Temporary (TEMP)
Read/Write
TEMP
Register: 0x20 (0xA0)
DMA FIFO (DFIFO)
Read/Write
BO
Registers
x
x
7
x
x
x
x
0
Temporary
This 32-bit register stores the Return instruction address
pointer from the Call instruction. The address pointer
stored in this register is loaded into the
Pointer (DSP)
executed. This address points to the next instruction to
execute. Do not write to this register while the
LSI53C825A is executing SCRIPTS.
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
Byte Offset Counter
These bits, along with bits [1:0] in the
(CTEST5)
transferred between the SCSI core and the DMA core. It
is used to determine the number of bytes in the DMA
FIFO when an interrupt occurs. These bits are unstable
while data is being transferred between the two cores.
Once the chip has stopped transferring data, these bits
are stable.
The
bytes transferred between the DMA core and the SCSI
core. The
number of bytes transferred across the host bus. The
x
x
DMA FIFO (DFIFO)
x
0
TEMP
x
DMA Byte Counter (DBC)
register, indicate the amount of data
x
x
register when a Return instruction is
0
x
BO
x
x
0
register counts the number of
x
x
x
0
x
register counts the
x
Chip Test Five
DMA SCRIPTS
x
0
x
x
x
[31:0]
0
0
x
[7:0]
0
x