LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 182

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-94
Registers: 0x54–0x55 (0xD4–0xD5)
SCSI Output Data Latch (SODL)
Read/Write
SODL
Registers: 0x58–0x59 (0xD8–0xD9)
SCSI Bus Data Lines (SBDL)
Read Only
SBDL
Registers
15
15
x
x
x
x
x
x
x
x
SCSI Output Data Latch
This register is used primarily for diagnostic testing or
programmed I/O operation. Data written to this register is
asserted onto the SCSI data bus by setting the Assert
Data Bus bit in the
This register is used to send data using programmed I/O.
Data flows through this register when sending data in any
mode. It is also used to write to the synchronous data
FIFO when testing the chip. The power-up value of this
register is indeterminate.
SCSI Bus Data Lines
This register contains the SCSI data bus status. Even
though the SCSI data bus is active low, these bits are
active high. The signal status is not latched and is a true
representation of exactly what is on the data bus at the
time the register is read. This register is used when
receiving data using programmed I/O. This register can
also be used for diagnostic testing or in the low level
mode. The power-up value of this register is
indeterminate.
If the chip is in the wide mode
(SCNTL3), bit 3 and
set) and
lanes are checked for parity regardless of phase. When
in a nondata phase, this causes a parity error interrupt to
be generated because upper byte lane parity is invalid.
x
x
x
x
SCSI Bus Data Lines (SBDL)
x
x
x
x
SODL
SBDL
SCSI Control One (SCNTL1)
x
x
SCSI Test Two
x
x
x
x
(SCSI Control Three
x
x
(STEST2), bit 2 are
is read, both byte
x
x
x
x
register.
x
x
[15:0]
[15:0]
0
x
0
x