LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 150

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-62
23
x
x
x
x
x
Register: 0x24–0x26 (0xA4–0xA6)
DMA Byte Counter (DBC)
Read/Write
DBC
Registers
x
x
x
x
DMA Byte Counter
This 24-bit register determines the number of bytes
transferred in a Block Move instruction. While sending
data to the SCSI bus, the counter is decremented as data
is moved into the DMA FIFO from memory. While
receiving data from the SCSI bus, the counter is
decremented as data is written to memory from the
LSI53C825A. The DBC counter is decremented each
time data is transferred on the PCI bus. It is decremented
by an amount equal to the number of bytes that are
transferred.
The maximum number of bytes that can be transferred in
any one Block Move command is 16,777,215 bytes. The
maximum value that can be loaded into the
Counter (DBC)
a Block Move and a value of 0x000000 is loaded into the
DMA Byte Counter (DBC)
interrupt occurs if the LSI53C825A is not in the target
mode, Command phase.
The
hold the least significant 24 bits of the first Dword of a
SCRIPTS fetch, and to hold the offset value during table
indirect I/O SCRIPTS. The power-up value of this register
is indeterminate.
x
x
DMA Byte Counter (DBC)
x
DBC
x
register is 0xFFFFFF. If the instruction is
x
x
x
register, an illegal instruction
x
x
register is also used to
x
x
x
DMA Byte
x
x
[23:0]
0
x