LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 293

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

A
A[6:0]
abort operation (ABRT)
aborted (ABRT)
absolute maximum stress ratings
AC characteristics
active termination
adder sum output (ADDER)
address and data signals
always wide SCSI (AWS)
arbitration
assert
B
base address register
bidirectional
big and little endian support
block move instructions
bridge support extensions (BSE[7:0])
burst
bus
byte
C
cache line size
call instruction
cap_ID (CID[7:0])
capabilities pointer (CP[7:0])
carry test
chained block moves
arbitration signals
in progress (AIP)
mode bits 1 and 0 (ARB[1:0])
priority encoder test (ART)
even SCSI parity (force bad parity) (AESP)
SATN/ on parity error (AAP)
SCSI
one (BARO[31:0])
one (BART[31:0])
zero - I/O (BARZ[31:0])
disable (BDIS)
length (BL[1:0])
length bit 2 (BL2)
opcode fetch enable (BOF)
fault (BF)
count
empty in DMA FIFO (FMT)
full in DMA FIFO (FFL[3:0])
offset counter (BO[7:0])
(CLS[7:0])
enable (CLSE)
SODL register
5-26
ACK/ signal (ACK)
ATN/ signal (ATN)
BSY/ signal (BSY)
C_D/ signal (C_D)
data bus (ADB)
I_O/ signal (I/O)
MSG/ signal (MSG)
REQ/ signal (REQ)
RST/ signal (RST)
SEL/ signal (SEL)
5-41
5-34
3-4
4-41
4-8
5-30
4-41
4-14
2-29
,
6-11
2-43
4-57
4-68
4-64
4-67
,
4-44
2-42
4-10
4-60
3-9
4-9
4-67
4-23
4-48
5-6
4-38
3-7
4-89
4-38
4-38
4-38
4-38
4-24
4-38
4-38
4-9
4-38
4-56
Index
4-70
2-19
,
4-12
,
4-40
4-86
,
,
,
,
4-52
4-66
,
4-52
,
4-22
4-39
4-39
4-39
4-40
4-39
6-2
4-39
4-20
4-40
4-17
4-24
chained mode (CHM)
chip
clear DMA FIFO (CLF)
clear instruction
clear SCSI FIFO (CSF)
clock
compare
configured
connected (CON)
D
data
data path
destination
differential mode
diffsens mismatch (DIFF)
DIFFSENS SCSI signal
direct
disable
disconnect instruction
DMA
SWIDE register
wide SCSI receive bit
wide SCSI send bit
revision level (V[3:0])
test five (CTEST5)
test four (CTEST4)
test one (CTEST1)
test six (CTEST6)
test three (CTEST3)
test two (CTEST2)
test zero (CTEST0)
type (TYP[3:0])
address incrementor (ADCK)
byte counter (BBCK)
conversion factor (CCF[2:0])
data
phase
as I/O (CIO)
as memory (CM)
(DATA[7:0])
acknowledge status (DACK)
compare mask
compare value
request status (DREQ)
structure address (DSA)
transfer direction (DDIR)
address
I/O-memory enable (DIOM)
DIFFSENS
direction control pins
operation
halt on parity error or ATN (target only) (DHP)
single initiator response (DSI)
byte counter (DBC)
command (DCMD)
control (DCNTL)
direction (DDIR)
FIFO
interrupt
5-21
(DF[7:0])
(DFIFO)
byte offset counter, bits [9:8] (BO[9:8])
empty (DFE)
size (DFS)
enable (DIEN)
5-35
2-24
5-35
5-26
2-28
3-12
4-17
5-16
4-56
4-53
4-60
4-24
4-59
5-36
5-36
4-79
2-43
4-60
,
4-68
4-40
4-53
4-26
5-15
4-60
,
4-67
5-19
4-59
4-53
4-62
4-52
4-57
4-55
2-42
4-61
4-52
4-91
6-3
4-50
4-54
4-59
3-10
4-54
4-47
2-42
4-54
4-48
4-53
4-65
4-29
4-54
4-59
4-91
4-60
4-24
IX-3