LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 161

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

UDC
RST
PAR
Register: 0x41 (0xC1)
SCSI Interrupt Enable One (SIEN1)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
(SIST1)
bit. For more information on interrupts refer to
Description.”
Operating Registers
7
x
register. An interrupt is masked by clearing the appropriate mask
x
Unexpected Disconnect
This condition only occurs in the initiator mode. It
happens when the target to which the LSI53C825A is
connected disconnects from the SCSI bus unexpectedly.
See the SCSI Disconnect Unexpected bit in the
Control Two (SCNTL2)
expected versus unexpected disconnects. Any discon-
nect in the low level mode causes this condition.
SCSI Reset Condition
Indicates assertion of the SRST/ signal by the
LSI53C825A or any other SCSI device. This condition is
edge-triggered, so multiple interrupts cannot occur
because of a single SRST/ pulse.
SCSI Parity Error
Indicates detection by the LSI53C825A of a parity error
while receiving or sending SCSI data. See the Disable
Halt on Parity Error or SATN/ Condition bits in the
Control One (SCNTL1)
when this condition is actually raised.
Residual data in SCSI FIFO – starting a transfer other
than synchronous data receive with data left in the
SCSI synchronous receive FIFO.
R
x
x
register for more information on
register for more information on
SCSI Interrupt Status One
3
x
Chapter 2, “Functional
STO
2
0
GEN
1
0
SCSI
HTH
SCSI
0
0
4-73
2
1
0