LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 98

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-10
31
x
x
x
x
x
x
x
Register: 0x18
RAM Base Address Two (Memory) SCRIPTS RAM
Read/Write
BART
Register: 0x2C
Subsystem Vendor ID (SSVID)
Read Only
SSVID
Registers
LSI53C825AE
LSI53C825A
x
15
1
0
x
1
0
x
x
1
0
x
1
0
Base Address Register Two
This register holds the memory base address of the
4 Kbyte internal RAM. The user can read this register
through the
the operating register set when bit 3 of the
(CTEST2)
Subsystem Vendor ID
This register supports subsystem identification, which
has a default value of 0x1000 in the LSI53C825AE
(Section 3.2, “MAD Bus
register, connect a 4.7 k
pin and V
MAD[6] and MAD[4] pins have internal pull-up resistors
and are sensed shortly after the deassertion of chip
reset. In revisions before Rev. G of the LSI53C825A, the
MAD[6] and MAD[4] pins do not support the SSID and
SSVID configurations, and only values of 0x0000 can be
found in the Subsystem Data register.
x
x
0
0
x
BART
x
0
0
SS
register is set.
x
Scratch Register B (SCRATCHB)
and leave the MAD[4] pin unconnected. The
0
0
x
x
0
0
SSVID
x
0
0
x
Programming”). To write to this
x
0
0
resistor between the MAD[6]
x
0
0
x
x
0
0
x
x
0
0
Chip Test Two
x
0
0
register in
x
x
0
0
[31:0]
[15:0]
x
0
0
0
0
0