LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 181

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Registers: 0x50–0x51 (0xD0–0xD1)
SCSI Input Data Latch (SIDL)
Read Only
SIDL
Operating Registers
15
x
x
x
x
Data Latch (SODL)
contained in SODL to be loaded into the FIFO. These
functions are summarized in the following table.
SCSI Input Data Latch
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery. Data
received from the SCSI bus can be read from this
register. Data can be written to the
Latch (SODL)
LSI53C825A by reading this register to allow loopback
testing. When receiving SCSI data, the data flows into
this register and out to the host FIFO. This register differs
from the
Input Data Latch (SIDL)
SCSI Bus Data Lines (SBDL)
what is currently on the SCSI data bus. Reading this
register causes the SCSI parity bit to be checked, and
causes a parity error interrupt if the data is not valid. The
power-up values are indeterminate.
x
Register
SODL0
SODL1
Name
SODL
x
SCSI Bus Data Lines (SBDL)
x
register and then read back into the
x
Operation
Register
Write
Write
Write
SIDL
x
register cause the entire word
x
contains latched data and the
x
always contains exactly
FIFO Bits
[15:0]
[15:8]
[7:0]
x
SCSI Output Data
x
register;
FIFO Function
x
Unload
Unload
None
SCSI
x
[15:0]
4-93
0
x