LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 94

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-6
R
DT[1:0]
DPR
R
NC
R
Registers
Reserved
DEVSEL/ Timing
These bits encode the timing of DEVSEL/. These are
encoded as:
0b00
0b01
0b10
0b11
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. In the LSI53C825A, 0b01 is supported.
Data Parity Reported
This bit is set when the following three conditions are
met:
Reserved
New Capabilities (NC)
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is Read Only,
and applies to the LSI53C825AE only.
Reserved
The bus agent asserted PERR/ itself or observed
PERR/ asserted and;
The agent setting this bit acted as the bus master for
the operation in which the error occurred and;
The Parity Error Response bit in the
register is set.
Fast
Medium
Slow
Reserved
Command
[10:9]
[7:5]
[3:0]
11
8
4