LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 200

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

5-16
SCSI SCRIPTS Instruction Set
Note:
Note:
None of the signals are set on the SCSI bus in Target
mode.
None of the signals are cleared on the SCSI bus in the
Target mode.
1. If the LSI53C825A is selected, it fetches the next
2. If reselected, the LSI53C825A fetches the next
3. If the CPU sets the SIGP bit in the
Wait Select Instruction
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the
(SOCL)
except for testing purposes. When the target bit is set,
the corresponding bit in the
register is also set. When the carry bit is set, the
corresponding bit in the Arithmetic Logic Unit (ALU) is
set.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
Control Latch (SOCL)
SATN/ except for testing purposes. When the target bit is
cleared, the corresponding bit in the
(SCNTL0)
cleared, the corresponding bit in the ALU is cleared.
Figure 5.3
instruction from the address pointed to by the
SCRIPTS Pointer (DSP)
instruction from the address pointed to by the 32-bit
jump address field stored in the
(DNAD)
Initiator mode when it is reselected.
(SSTAT0)
Select instruction and fetches the next instruction from
the address pointed to by the 32-bit jump address
field stored in the
register are set. Do not set SACK/ or SATN/
register is cleared. When the carry bit is
illustrates the I/O Instruction register.
register. Manually set the LSI53C825A to
register, the LSI53C825A aborts the Wait
DMA Next Address (DNAD)
register. Do not set SACK/ or
SCSI Output Control Latch
SCSI Control Zero (SCNTL0)
register.
DMA Next Address
SCSI Control Zero
SCSI Output
SCSI Status Zero
register.
DMA