LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 128

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-40
MSG
C/D
I/O
This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. The resulting read data is synchronized before being
presented to the PCI bus to prevent parity errors from being passed to
the system. This register is used for diagnostics testing or operation in
the low level mode.
Register: 0x0C (0x8C)
DMA Status (DSTAT)
Read Only
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C825A stack interrupts). The DIP bit in
the
DMA interrupt conditions individually through the
(DIEN)
When performing consecutive 8-bit reads of the
SCSI Interrupt Status Zero (SIST0),
(SIST1)
periods between the reads to ensure that the interrupts clear properly.
See
interrupts.
DFE
Registers
DFE
Interrupt Status (ISTAT)
7
1
Chapter 2, “Functional Description,”
register.
registers (in any order), insert a delay equivalent to 12 CLK
MDPE
6
0
Assert SCSI MSG/ Signal
Assert SCSI C_D/ Signal
Assert SCSI I_O/ Signal
DMA FIFO Empty
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
BF
5
0
register is also cleared. It is possible to mask
ABRT
4
0
and
SSI
3
0
for more information on
SCSI Interrupt Status One
SIR
DMA Status
2
0
DMA Interrupt Enable
R
1
x
(DSTAT),
IID
0
0
2
1
0
7