LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 153

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

31
x
x
x
x
x
x
x
Registers: 0x34–0x37 (0xB4–0xB7)
Scratch Register A (SCRATCHA)
Read/Write
SCRATCHA
Register: 0x38 (0xB8)
DMA Mode (DMODE)
Read/Write
BL[1:0]
Operating Registers
x
x
7
0
BL[1:0]
x
x
x
6
0
Scratch Register A
This is a general purpose, user-definable scratch pad
register. Apart from CPU access, only register read/write
and memory moves into the SCRATCH register alter its
contents. The LSI53C825A cannot fetch SCRIPTS
instructions from this location. When bit 3 in the
Two (CTEST2)
memory mapped base address of the operating registers.
Setting
base address to appear in this register; any information
that was previously in the register will remain intact. Any
writes to this register while
is set will pass through to the actual
(SCRATCHA)
register is indeterminate.
Burst Length
These bits control the maximum number of Dwords
transferred per bus ownership, regardless of whether the
transfers are back-to-back, burst, or a combination of
both. This value is also independent of the width (64 or
32 bits) of the data transfer on the PCI bus. The
LSI53C825A asserts the Bus Request (REQ/) output
when the DMA FIFO can accommodate a transfer of at
least one burst threshold of data. Bus Request (REQ/) is
also asserted during start-of-transfer and end-of-transfer
cleanup and alignment, even if less than a full burst of
x
x
SIOM
SCRATCHA
x
5
0
Chip Test Two
x
x
DIOM
register. The power-up value of this
x
register is set, this register contains the
4
0
x
x
(CTEST2), bit 3 only causes the
x
ER
3
0
x
Chip Test Two
x
ERMP
x
2
0
x
Scratch Register A
x
x
(CTEST2), bit 3
BOF
1
0
x
x
Chip Test
x
MAN
[31:0]
0
0
x
[7:6]
4-65
0
x