DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 1140

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Appendix B Internal I/O Registers
BCRL—Bus Control Register L
Rev.6.00 Sep. 27, 2007 Page 1108 of 1268
REJ09B0220-0600
Bit
Initial value
Read/Write
:
:
:
BRLE
R/W
Bus Release Enable
7
0
0
1
Note: * The BREQO output pin can be switched between
External bus release disabled
External bus release enabled
BREQO Pin Enable
0
1
BREQOE
R/W
6
0
BREQO output disabled
BREQO * output enabled
PF
2
and P5
External Addresses H'010000 to H'03FFFF Enable
Notes: 1. Do not access a reserved area.
0
1
EAE
R/W
5
1
3
• In the H8S/2329B, H8S/2328
• In the H8S/2327, addresses H'010000 to H'01FFFF are on-chip ROM,
• In the H8S/2323, addresses H'010000 to H'03FFFF are a reserved area
Addresses H'010000 to H'03FFFF
in external expanded mode or reserved area
by means of BREQOPS.
2. Address H'010000 to H'03FFFF in the H8S/2328.
3. H8S/2328B in flash memory version.
H'03FFFF
and addresses H'020000 to H'03FFFF are a reserved area
Address H'010000 to H'05FFFF in the H8S/2329B.
Address H'010000 to H'07FFFF in the H8S/2326.
Reserved
Only 1 should be written to this bit
R/W
—
4
1
*2
are on-chip ROM
DACK Timing Select
Note: In the H8S/2321 this bit is reserved and should only
0
1
DDS
R/W
3
1
H'FED5
When DMAC single address transfer is performed in
DRAM space, full access is always executed. DACK
signal goes low from Tr or T1 cycle
Burst access is possible when DMAC single address
transfer is performed in DRAM space. DACK signal
goes low from Tc1 or T2 cycle
be written with 1.
Reserved
Only 1 should be written to this bit
R/W
*3
—
2
1
, and H8S/2326, addresses H'010000 to
*2
are external addresses
Write Data Buffer Enable
WDBE
0
1
R/W
*2
1
0
in single-chip mode
Write data buffer function
not used
Write data buffer function
used
WAIT Pin Enable
Note: * The WAIT input pin
0
1
WAITE
Wait input by WAIT
pin * disabled
Wait input by WAIT
pin * enabled
R/W
can be switched
between PF
P5
WAITPS.
0
0
3
Bus Controller
*1
by means of
2
and
*1