DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 955

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

21.2.2
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is
disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to
the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the
division ratio. As the frequency of φ changes, the following points must be noted.
• The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the
• All internal modules basically operate on φ. Note, therefore, that time processing involving the
Bit
Initial value :
R/W
guaranteed operation range of clock cycle time tcyc given in the AC timing table in the
Electrical Characteristics section. Ensure that φ min = 2 MHz, and the condition φ < 2 MHz
does not arise.
timers, the SCI, etc., will change when the division ratio changes. The wait time when software
standby is cleared will also change in line with a change in the division ratio.
System Clock Control Register (SCKCR)
Normal
Operating Mode
φ output (Initial value)
Fixed high
:
:
PSTOP
R/W
7
0
R/W
—
6
0
Sleep Mode
φ output
Fixed high
R/W
DIV
5
0
Description
—
—
4
0
Software
Standby Mode
Fixed high
Fixed high
Rev.6.00 Sep. 27, 2007 Page 923 of 1268
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3
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Section 21 Power-Down Modes
SCK2
R/W
2
0
Hardware
Standby Mode
High impedance
High impedance
REJ09B0220-0600
SCK1
R/W
1
0
SCK0
R/W
0
0