DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 245

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

6.10.5
Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a
transition is made to sleep mode when either of these settings has been made.
6.11
6.11.1
The chip has a bus arbiter that arbitrates bus master operations.
There are three bus masters, the CPU, DTC, and DMAC * , which perform read/write operations
when they have possession of the bus. Each bus master requests the bus by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus request acknowledge signal. The selected bus master then takes possession of the
bus and begins its operation.
Note: * The DMAC is not supported in the H8S/2321.
6.11.2
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled.
The order of priority of the bus masters is as follows:
An internal bus access by an internal bus master, external bus release, and refreshing * , can be
executed in parallel.
In the event of simultaneous external bus release request, refresh request * , and internal bus master
external access request generation, the order of priority is as follows:
Usage Note
Bus Arbitration
Overview
Operation
(High) DMAC * > DTC > CPU (Low)
(High) Refresh * > External bus release (Low)
(High) External bus release > Internal bus master external access (Low)
Rev.6.00 Sep. 27, 2007 Page 213 of 1268
Section 6 Bus Controller
REJ09B0220-0600