DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 264

IC H8S MCU FLASH 256K 128QFP

DF2328BVF25V

Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2328BVF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 DMA Controller (Not Supported in the H8S/2321)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In short address mode, channels 0A and 0B can be used as independent channels.
Bit 14
FAE0
0
1
Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for
transfer in dual address mode or single address mode.
This bit is invalid in full address mode.
Bit 13
SAE1
0
1
Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for
transfer in dual address mode or single address mode.
This bit is invalid in full address mode.
Bit 12
SAE0
0
1
Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when
DMA transfer is performed, of the internal interrupt source selected by the data transfer factor
setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor
setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal
interrupt source selected by the data transfer factor setting does not issue an interrupt request to the
CPU or DTC.
Rev.6.00 Sep. 27, 2007 Page 232 of 1268
REJ09B0220-0600
Description
Short address mode
Full address mode
Description
Transfer in dual address mode
Transfer in single address mode
Description
Transfer in dual address mode
Transfer in single address mode
(Initial value)
(Initial value)
(Initial value)

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