DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 943

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

20.1
The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-
speed clock divider, and a bus master clock selection circuit.
In the chip, the CPG has a medium-speed mode in which the bus master runs on a medium-speed
clock and the other supporting modules run on the high-speed clock, and a function that allows the
medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
A clock from φ/2 to φ/32 can be selected.
20.1.1
Figure 20.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Note: * The DMAC is not supported in the H8S/2321.
Overview
Block Diagram
Oscillator
Figure 20.1 Block Diagram of Clock Pulse Generator
Section 20 Clock Pulse Generator
adjustment
circuit
Duty
System clock
to φ pin
speed clock
Medium-
divider
Rev.6.00 Sep. 27, 2007 Page 911 of 1268
φ/2 to φ/32
Internal clock
to supporting
modules
Section 20 Clock Pulse Generator
DIV
Bus master
selection
SCKCR
circuit
clock
REJ09B0220-0600
Bus master clock
to CPU, DTC,
and DMAC*
SCK2 to SCK0