DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 22

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

10.7 Usage Notes ...................................................................................................................... 521
Section 11 Programmable Pulse Generator (PPG) ............................................531
11.1 Overview........................................................................................................................... 531
11.2 Register Descriptions ........................................................................................................ 535
11.3 Operation........................................................................................................................... 545
11.4 Usage Notes ...................................................................................................................... 554
Section 12 8-Bit Timers.....................................................................................557
12.1 Overview........................................................................................................................... 557
12.2 Register Descriptions ........................................................................................................ 560
Rev.6.00 Sep. 27, 2007 Page xx of xxx
REJ09B0220-0600
11.1.1 Features................................................................................................................ 531
11.1.2 Block Diagram ..................................................................................................... 532
11.1.3 Pin Configuration................................................................................................. 533
11.1.4 Registers............................................................................................................... 534
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 535
11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 536
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 537
11.2.4 Notes on NDR Access ......................................................................................... 537
11.2.5 PPG Output Control Register (PCR).................................................................... 539
11.2.6 PPG Output Mode Register (PMR)...................................................................... 541
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 543
11.2.8 Port 2 Data Direction Register (P2DDR)............................................................. 544
11.2.9 Module Stop Control Register (MSTPCR) .......................................................... 544
11.3.1 Overview.............................................................................................................. 545
11.3.2 Output Timing...................................................................................................... 546
11.3.3 Normal Pulse Output............................................................................................ 547
11.3.4 Non-Overlapping Pulse Output............................................................................ 549
11.3.5 Inverted Pulse Output .......................................................................................... 552
11.3.6 Pulse Output Triggered by Input Capture ............................................................ 553
11.4.1 Operation of Pulse Output Pins............................................................................ 554
11.4.2 Note on Non-Overlapping Output........................................................................ 554
12.1.1 Features................................................................................................................ 557
12.1.2 Block Diagram ..................................................................................................... 558
12.1.3 Pin Configuration................................................................................................. 559
12.1.4 Register Configuration......................................................................................... 559
12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 560
12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 560
12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 561
12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 561