DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 469

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
PG
Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port G Register (PORTG)
Note: * Determined by state of pins PG
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as
PGDDR and PGDR are initialized. PORTG retains its prior state in software standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
0
).
:
:
:
:
Undefined Undefined Undefined
Undefined Undefined Undefined
—
—
—
—
7
7
—
—
—
—
6
6
4
to PG
4
to PG
—
—
—
—
5
5
0
) must always be performed on PGDR.
0
.
PG4DR
PG4
R/W
— *
R
4
0
4
Rev.6.00 Sep. 27, 2007 Page 437 of 1268
PG3DR
R/W
PG3
— *
R
3
0
3
PG2DR
R/W
PG2
— *
R
2
0
2
Section 9 I/O Ports
PG1DR
REJ09B0220-0600
R/W
PG1
— *
R
0
1
1
4
PG0DR
to
PG0
R/W
— *
R
0
0
0