DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 373
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed
using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output
trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the
chain transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because
clearing of the activation source and interrupt generation at the end of the specified number of
transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0).
[1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing
[2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing
[3] Locate the TPU transfer register information consecutively after the NDR transfer register
[4] Set the start address of the NDR transfer register information to the DTC vector address.
[5] Set the bit corresponding to TGIA in DTCER to 1.
[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
[7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
[8] Set the CST bit in TSTR to 1, and start the TCNT count operation.
[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
[10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0
= 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in
DAR, and the data table size in CRA. CRB can be set to any value.
information.
interrupt with TIER.
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Wrap-up processing should be performed in the interrupt handling routine.
Rev.6.00 Sep. 27, 2007 Page 341 of 1268
Section 8 Data Transfer Controller
REJ09B0220-0600
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