DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 331

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 7.35 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
Address bus
DMA control
Channel 0A
Channel 0B
Channel 1
HWR
LWR
RD
φ
release
Idle
Bus
Request clear
Read
DMA read
Request
hold
Request
hold
Figure 7.35 Example of Multi-Channel Transfer
Write
Channel 0A
transfer
Selection
DMA write
selection
Non-
Idle
Section 7 DMA Controller (Not Supported in the H8S/2321)
release
Request clear
Bus
Read
DMA read
Request
hold
Write
Channel 0B
transfer
Rev.6.00 Sep. 27, 2007 Page 299 of 1268
Selection
DMA write
Idle
release
Request clear
Bus
Read
DMA read
Channel 1 transfer
Write
REJ09B0220-0600
DMA write
Read
DMA
read