DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 794

IC H8S MCU FLASH 256K 128QFP

DF2328BVF25V

Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2328BVF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 ROM
Notes on Use of Boot Mode
• When the chip comes out of reset in boot mode, it measures the low-level period of the input at
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'FF8400 to H'FFFBFF),
Rev.6.00 Sep. 27, 2007 Page 762 of 1268
REJ09B0220-0600
Note: * The boot program area cannot be used until a transition is made to the execution state
the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes
approximately 100 states before the chip is ready to measure the low-level period of the RxD1
pin.
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
for the programming control program transferred to RAM. Note that the boot program
remains stored in this area after a branch is made to the programming control program.
Figure 19.12 RAM Areas in Boot Mode
H'FF7C00
H'FF83FF
H'FFFBFF
control program
Boot program
Programming
(30 kbytes)
(2 kbytes)
area*
area

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