HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet
HD6473937RXV
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HD6473937RXV Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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H8/3937 Series, H8/3937R Series ADE-602-218 Rev. 1.0 2/27/01 Hitachi Ltd. H8/3937 HD6433937, HD6473937 H8/3936 HD6433936 H8/3935 HD6433935 H8/3937R HD6433937R, HD6473937R H8/3936R HD6433936R H8/3935R HD6433935R Hardware Manual ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3937 Series and H8/3937R Series include, a FLEX™ ...
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Section 1 Overview ........................................................................................................... 1.1 Overview............................................................................................................................ 1.2 Internal Block Diagram ..................................................................................................... 1.3 Pin Arrangement and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ Section 2 CPU ..................................................................................................................... 13 2.1 Overview............................................................................................................................ 13 2.1.1 Features ................................................................................................................ 13 2.1.2 Address Space ...................................................................................................... ...
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Memory Map ..................................................................................................................... 2.9 Application Notes.............................................................................................................. 50 2.9.1 Notes on Data Access........................................................................................... 2.9.2 Notes on Bit Manipulation ................................................................................... 2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 58 Section 3 Exception Handling 3.1 Overview............................................................................................................................ 59 3.2 Reset .................................................................................................................................. 59 ...
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Standby Mode.................................................................................................................... 105 5.3.1 Transition to Standby Mode ................................................................................. 105 5.3.2 Clearing Standby Mode........................................................................................ 105 5.3.3 Oscillator Settling Time after Standby Mode is Cleared...................................... 105 5.3.4 Standby Mode Transition and Pin States.............................................................. 106 5.3.5 Notes on External Input Signal ...
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Block Diagram...................................................................................................... 131 Section 8 I/O Ports ............................................................................................................ 133 8.1 Overview............................................................................................................................ 133 8.2 Port 1.................................................................................................................................. 135 8.2.1 Overview .............................................................................................................. 135 8.2.2 Register Configuration and Description............................................................... 135 8.2.3 Pin Functions........................................................................................................ 140 8.2.4 Pin States .............................................................................................................. 142 8.2.5 MOS Input Pull-Up ...
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Port 8.................................................................................................................................. 168 8.9.1 Overview .............................................................................................................. 168 8.9.2 Register Configuration and Description............................................................... 168 8.9.3 Pin Functions........................................................................................................ 169 8.9.4 Pin States .............................................................................................................. 169 8.10 Port 9.................................................................................................................................. 170 8.10.1 Overview .............................................................................................................. 170 8.10.2 Register Configuration and Description............................................................... 170 8.10.3 Pin Functions........................................................................................................ ...
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Timer G.............................................................................................................................. 215 9.5.1 Overview .............................................................................................................. 215 9.5.2 Register Descriptions............................................................................................ 217 9.5.3 Noise Canceler...................................................................................................... 221 9.5.4 Operation .............................................................................................................. 223 9.5.5 Application Notes................................................................................................. 227 9.5.6 Timer G Application Example ............................................................................. 232 9.6 Watchdog Timer................................................................................................................ 233 9.6.1 Overview .............................................................................................................. 233 9.6.2 ...
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Interrupts............................................................................................................................ 323 11.5 Typical Use........................................................................................................................ 323 11.6 Application Notes.............................................................................................................. 327 Section 12 FLEX™ Roaming Decoder II 12.1 Overview............................................................................................................................ 329 12.1.1 Features ................................................................................................................ 329 12.1.2 System Block Diagram......................................................................................... 330 12.1.3 Functional Block Diagram ................................................................................... 332 12.2 SPI Packets ........................................................................................................................... 333 ...
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SPI Timing............................................................................................................ 387 12.6.2 Start-up Timing .................................................................................................... 389 12.6.3 Reset Timing ........................................................................................................ 390 Section 13 Electrical Characteristics 13.1 Absolute Maximum Ratings.............................................................................................. 391 13.2 Electrical Characteristics ................................................................................................... 392 13.2.1 Power Supply Voltage and Operating Range....................................................... 392 13.2.2 DC Characteristics................................................................................................ 394 ...
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Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. The H8/3937 and H8/3937R Series are H8/300L Series microcomputers with an on-chip FLEX™ ...
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Table 1-1 Features Item Description CPU High-speed H8/300L CPU General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed Max. operating speed: 5 MHz Add/subtract: 0.4 s (operating at 5 MHz) Multiply/divide: 2.8 s ...
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Item Description Memory Large on-chip memory H8/3935, H8/3935R: 40-kbyte ROM, 2-kbyte RAM H8/3936, H8/3936R: 48-kbyte ROM, 2-kbyte RAM H8/3937, H8/3937R: 60-kbyte ROM, 2-kbyte RAM I/O ports 67 pins 59 I/O pins 8 input pins 5 internal I/O 1 internal input ...
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Item Description A/D converter Successive approximations using a resistance ladder 8-channel analog input pins Conversion time: 31/ø or 62/ø per channel FLEX™ On-chip FLEX™ decoder II decoder II Conforms to FLEX™ protocol revision 1.9 Decoding capability: 1600, 3200, 6400 bits/second ...
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Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3937 Series and H8/3937R Series. P1 /TMOW 0 P1 /TMOFL 1 P1 /TMOFH 2 P1 /TMIG 3 P1 /IRQ /ADTRG /IRQ /TMIC ...
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Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3937 Series and H8/3937R Series pin arrangement is shown in figure 1- S0/IFIN 81 CLKOUT 82 TESTD 83 DX2 84 DX1 ...
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Pin Functions Table 1-2 outlines the pin functions of the H8/3937 Series and H8/3937R Series. Table 1-2 Pin Functions Pin No. TFP-100B Type Symbol TFP-100G Power source pins ...
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Pin No. TFP-100B Type Symbol TFP-100G IRQ Interrupt 19 1 IRQ pins 20 2 IRQ 21 3 IRQ 18 4 WKP WKP 0 Internal IRQ IRQ – interrupt pin Timer pins TMOW 14 ...
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Pin No. TFP-100B Type Symbol TFP-100G I/O ports ...
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Pin No. TFP-100B Type Symbol TFP-100G Serial RXD 62 32 communi- cation TXD 63 32 interface (SCI) SCK 61 32 Internal serial SI – 1 communi- cation SO – 1 interface (SCI) SCK – ...
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Pin No. TFP-100B Type Symbol TFP-100G FLEX™ CLKOUT 82 decoder II SYMCLK IFIN 81 I/O Name and Functions Output Clock output: 38.4 kHz or 40 kHz clock output (derived from on-chip ...
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12 ...
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Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. General-register architecture ...
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Address Space The H8/300L CPU supports an address space kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H ...
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Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For ...
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Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. Bit manipulation instructions operate on 1-bit data specified as bit byte operand ( ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2-4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at ...
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Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. Address Modes 1 Register direct 2 Register indirect ...
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The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV for MOV.W. For MOV.W, the original contents of ...
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If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. ...
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Table 2-2 Effective Address Calculation 23 ...
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24 ...
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25 ...
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Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data ...
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Notation (EAd), <EAd> (EAs), <EAs> CCR #IMM disp + – : < > General register (destination) General register (source) General register Destination operand Source operand Condition ...
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Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* MOV B/W POP W PUSH W Notes: * Size: Operand size B: Byte W: Word ...
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Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 Data Transfer ...
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Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction Size* ADD B/W SUB ADDX B SUBX INC B DEC ADDS W SUBS DAA B DAS MULXU B DIVXU B CMP B/W NEG B Notes: * ...
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Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction Size* AND XOR B NOT B Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 ...
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Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions Notation: op: Operation field rm, rn: Register field IMM: Immediate data ...
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Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* BSET B BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Notes: * ...
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Instruction Size* BXOR B BIXOR B BLD B BILD B BST B BIST B Notes: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for details. 34 Function C (<bit-No.> ...
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Notation: op: Operation field rm, rn: Register ...
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Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont IMM ...
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Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Bcc — JMP — BSR — JSR — RTS — Function Branches to the designated address if condition ...
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Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes disp ...
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System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* RTE — SLEEP — LDC B STC B ANDC B ORC B XORC B NOP ...
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Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code ...
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Notation: op: Operation field Figure 2-10 Block Data Transfer Instruction Code ...
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Basic Operational Timing CPU operation is synchronized by a system clock (ø subclock (ø clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is ...
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Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions ...
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Three-state access to on-chip peripheral modules ø or ø SUB Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access) 44 Bus ...
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CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt ...
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Reset state Reset occurs Program halt state 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one ...
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Memory Map The memory map of the H8/3935 and H8/3935R is shown in figure 2-16 (1), that of the H8/3936 and H8/3936R in figure 2-16 (2), and that of the H8/3937 and H8/3937R in figure 2-16 (3). H'0000 H'0029 ...
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H'0000 H'0029 H'002A H'BFFF H'F780 H'FF7F H'FF90 H'FFFF Figure 2-16 (2) H8/3936 and H8/3936R Memory Map 48 Interrupt vector area On-chip ROM Not used On-chip RAM Not used Internal I/O registers (112 bytes) 48 kbytes (49152 bytes) 2048 bytes ...
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H'0000 Interrupt vector area H'0029 H'002A On-chip ROM H'EDFF Not used H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (3) H8/3937 and H8/3937R Memory Map 60 kbytes (60928 bytes) 2048 bytes 49 ...
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Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas ...
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H'0000 Interrupt vector area (42 bytes) H'0029 H'002A On-chip ROM * H'9FFF Not used H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Notes: The H8/3935 and H8/3935R are shown as an example. * The address ...
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Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers ...
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Example 2: BSET instruction executed designating port 3 P3 and P3 are designated as input pins, with a low-level signal input signal The remaining pins example, the BSET instruction is used ...
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To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. ...
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Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 high-level signal The remaining pins signals. In this ...
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To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. ...
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Table 2-12 lists the pairs of registers that share identical addresses. Table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers with Shared Addresses Register Name Timer counter and timer load register C 1 Port data register 1* ...
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Notes on Use of the EEPMOV Instruction The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by R6 ...
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Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3937 Series and H8/3937R Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Exception Handling Types ...
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When system power is turned on or off, the RES pin should be held low. Figure 3-1 shows the reset sequence starting from RES input. RES ø Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) ...
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Interrupts 3.3.1 Overview The interrupt sources that initiate interrupt exception handling comprise 12 external interrupts (WKP to WKP , IRQ to IRQ internal IRQ interrupt. Table 3-2 shows the interrupt sources, their priorities, and their vector ...
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Table 3-2 Interrupt Sources and Their Priorities Interrupt Source Interrupt RES Reset IRQ IRQ 0 0 IRQ IRQ 1 1 IRQ IRQ 2 2 IRQ IRQ 3 3 IRQ IRQ 4 4 WKP WKP 0 0 WKP WKP 1 1 ...
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Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Interrupt Control Registers Name IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 1 Interrupt request register 2 Wakeup interrupt ...
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Bit 3: IRQ edge select (IEG3) 3 Bit 3 selects the input sensing of the IRQ Bit 3 IEG3 Description Falling edge of IRQ 0 Rising edge of IRQ 1 Bit 2: IRQ edge select (IEG2) 2 Bit 2 selects ...
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Interrupt enable register 1 (IENR1) Bit 7 IENTA IENS1 Initial value 0 Read/Write R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer ...
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Bits IRQ to IRQ interrupt enable (IEN4 to IEN0 Bits enable or disable IRQ Bit n IENn Description Disables interrupt requests from pin IRQn 0 Enables interrupt requests from pin IRQn 1 ...
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Bit 4: Timer G interrupt enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests. Bit 4 IENTG Description 0 Disables timer G interrupt requests 1 Enables timer G interrupt requests Bit 3: Timer FH ...
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Interrupt request register 1 (IRR1) Bit 7 IRRTA IRRS1 Initial value 0 R/(W) * R/(W) * Read/Write Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding ...
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Bits IRQ to IRQ interrupt request flags (IRRI4 to IRRI0 Bit n IRRIn Description 0 Clearing conditions: When IRRIn = cleared by writing 0 1 Setting conditions: When pin IRQn is designated ...
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Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD Description 0 Clearing conditions: When IRRAD = cleared by writing 0 1 Setting conditions: When A/D conversion is completed and ADSF is cleared ...
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Bit 1: Timer C interrupt request flag (IRRTC) Bit 1 IRRTC Description 0 Clearing conditions: When IRRTC cleared by writing 0 1 Setting conditions: When the timer C counter value overflows (from H'FF to H'00) or underflows ...
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Wakeup Edge Select Register (WEGR) Bit 7 WKEGS7 WKEGS6 Initial value 0 Read/Write R/W WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H' reset. Bit ...
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When these pins are designated as pins IRQ designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN1 to ...
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Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance. External or internal interrupts External interrupts or internal interrupt enable signals ...
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If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The PC value pushed onto ...
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Program execution state IRRI0 = 1 Yes IEN0 = 1 Yes Yes PC contents saved CCR contents saved I 1 Branch to interrupt handling routine Notation: PC: Program counter CCR: Condition code register I: I bit of ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling Notation Upper 8 bits of program counter (PC Lower 8 bits of ...
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Figure 3-5 Interrupt Sequence ...
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Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States Item Waiting time for completion of ...
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Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3937 Series and H8/3937R Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in ...
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Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port ...
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Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions When PMR1 bit IRQ4 is changed from while pin IRQ IRR1 IRRI4 bit IEG4 = 0. When PMR1 ...
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CCR I bit Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 CCR I bit Figure 3-7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure 3.4.3 Notes on Interrupt Request Flag Clearing Methods ...
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84 ...
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Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator ...
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System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator providing external clock input. 1. Connecting a crystal oscillator Figure 4-2 shows a typical method of ...
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Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator OSC OSC Figure 4-4 Typical Connection to Ceramic Oscillator 3. Notes on board design When generating ...
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External clock input method Connect an external clock signal to pin OSC typical connection. OSC 1 OSC 2 Figure 4-6 External Clock Input (Example) Frequency Duty cycle Caution When a crystal or ceramic oscillator element is connected, circuit constants ...
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Subclock Generator 1. Connecting a 76.8-kHz/160-kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 76.8-kHz/160-kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 3. notes on board ...
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External clock input Connect the external clock to the Figure 4-10 Pin Connection when Inputting External Clock Frequency Duty 90 pin and leave the DX pin open, as shown in figure 4-10 ...
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Prescalers The H8/3937 Series and 3937R Series are equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler 13-bit counter using the system clock (ø) as its input clock. Its prescaled ...
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Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT™ versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending ...
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Oscillation waveform (OSC2) System clock (ø) Oscillation settling time Standby mode, Operating watch mode, mode or subactive mode Figure 4-11 Oscillation Settling Standby Time When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and ...
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Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding ...
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Section 5 Power-Down Modes 5.1 Overview The H8/3937 Series and H8/3937R Series have nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the eight ...
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Reset state Program halt state Standby mode *4 *1 SLEEP instruction Watch mode Mode Transition Conditions (1) LSON MSON SSBY TMA3 ...
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Table 5-2 Internal State in Each Operating Mode Active Mode High- Function Speed System clock oscillator Functions Subclock oscillator Functions CPU Instructions Functions operations RAM Registers I/O ports IRQ IRQ Functions 0 0 interrupt External IRQ Functions 1 interrupts IRQ ...
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System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 System Control Registers Name System control register 1 System control register 2 1. System control register 1 (SYSCR1) Bit 7 ...
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Bits Standby timer select (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due ...
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Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose ø /128, ø OSC (medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or subactive mode. Bit ...
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Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after ...
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Bits 1 and 0: Subactive mode clock select (SA1, SA0) These bits select the CPU clock rate (ø cannot be modified in subactive mode. Bit 1 Bit 0 SA1 SA0 Description 0 0 ø ø /4 ...
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Sleep Mode 5.2.1 Transition to Sleep Mode 1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared ...
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Clock Frequency in Sleep (Medium-Speed) Mode Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1. 104 ...
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Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared ...
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Table 5-4 Clock Frequency and Settling Time (times are in ms) STS2 STS1 STS0 When an ...
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Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ or WKP is input, both the high- and low-level widths ...
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Active (high-speed, Operating medium-speed) mode mode or subactive mode ø or ø SUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Figure 5-3 External Input Signal Capture when Signal Changes ...
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Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA ...
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Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to ...
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Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep ...
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Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared ...
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Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program ...
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Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and ...
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Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal processing states) } exception handling execution states) (t Example: Direct transition time = ( 16t CPU operating clock) Notation OSC clock ...
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Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and ...
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Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock ...
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Table 5-5 Setting and Clearing Module Standby Mode by Clock Stop Register Register Name Bit Name CKSTPR1 TACKSTP TCCKSTP TFCKSTP TGCKSTP ADCKSTP S1CKSTP S32CKSTP S31CKSTP Table 5-5 Setting and Clearing Module Standby Mode by Clock Stop Register (cont) Register Name ...
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Overview The H8/3935 and H8/3935R have 40 kbytes of mask ROM, the H8/3936 and H8/3936R have 48 kbytes of mask ROM, and the H8/3937 and H8/3937R have 60 kbytes of mask ROM on-chip. The ROM is connected to the ...
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PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 ...
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H8/3937, H8/3937R TFP-100B, Pin TFP-100G RES ...
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Address in MCU mode Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If programming is ...
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Programming The write, verify, and other modes are selected as shown in table 6-3 in PROM mode. Table 6-3 Mode Selection in PROM Mode (H8/3937, H8/3937R Mode Write L H Verify L L Programming L L disabled ...
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Yes Error Figure 6-4 High-Speed, High-Reliability Programming Flow Chart 124 Start Set write/verify mode V = 6 Address = Write ...
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Table 6-4 and table 6-5 give the electrical characteristics in programming mode. Table 6-4 DC Characteristics (Conditions 6 Item Input high OE, CE, PGM level voltage ...
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Table 6-5 AC Characteristics (Conditions 6 Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP Programming pulse width ...
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Figure 6-5 shows a PROM write/verify timing diagram. Address t AS Data Input data VPS + VCS CES PGM ...
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Programming Precautions Use the specified programming voltage and timing. The programming voltage in PROM mode (V permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 ...
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Reliability of Programmed Data A highly effective way to improve data retention characteristics is to bake the programmed chips at 150 C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to ...
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130 ...
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Overview The H8/3937 Series and H8/3937R Series have 2 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 ...
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132 ...
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Overview The H8/3937 Series and H8/3937R Series are provided with six 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, and one 8-bit input-only port. Also provided are one internal 5-bit I/O port and one internal 1-bit ...
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Port Description Port 3 8-bit I/O port MOS input pull-up option Port 4 1-bit input internal port 3-bit I/O port Port 5 8-bit I/O port MOS input pull-up option Port 6 8-bit I/O port MOS input pull-up option Port 7 ...
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Port 1 8.2.1 Overview Port 8-bit I/O port. Figure 8-1 shows its pin configuration. 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration. Table 8-2 Port 1 Registers Name Port data register ...
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Port data register 1 (PDR1) Bit Initial value 0 Read/Write R/W PDR1 is an 8-bit register that stores data for port 1 pins P1 bits are set to 1, the values stored in PDR1 are read, ...
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Port mode register 1 (PMR1) Bit 7 IRQ3 Initial value 0 Read/Write R/W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7: P1 ...
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Bit 4: P1 /IRQ /ADTRG pin function switch (IRQ4 This bit selects whether pin P1 Bit 4 IRQ4 Description 0 Functions as P1 Functions as IRQ 1 Note: For details of ADTRG pin setting, see 12.3.2, Start of ...
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Bit 0: P1 /TMOW pin function switch (TMOW) 0 This bit selects whether pin P1 Bit 0 TMOW Description 0 Functions Functions as TMOW output pin /TMOW is used as P10 or as TMOW. 0 I/O pin ...
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Pin Functions Table 8-3 shows the port 1 pin functions. Table 8-3 Port 1 Pin Functions Pin Pin Functions and Selection Method P1 /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in ...
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Pin Pin Functions and Selection Method P1 /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1. 3 TMIG PCR1 Pin function P1 /TMOFH The pin function depends on bit TMOFH in PMR1 and bit ...
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Pin States Table 8-4 shows the port 1 pin states in each operating mode. Table 8-4 Port 1 Pin States Pins Reset P1 /IRQ /TMIF High /IRQ impedance /IRQ /TMIC ...
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Port 2 [Chip Internal I/O Port] 8.3.1 Overview Port 5-bit I/O internal port. Figure 8-2 shows its functional configuration. Port internal function that performs interfacing to the FLEX™ decoder incorporated in the chip. ...
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Port data register 2 (PDR2) Bit 7 — Initial value 0 Read/Write — PDR2 is an 8-bit register that stores data for port 2 pins P2 bits are set to 1, the values stored in PDR2 are read directly. ...
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Bits and 3: Reserved bits Bits and 3 are reserved; they are always read as 1 and cannot be modified. Bit 5: P2 /SO pin PMOS control (POF1 This bit controls the ...
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Port mode register 4 (PMR4) Bit 7 — Initial value 0 Read/Write — PMR4 is an 8-bit read/write register that controls whether individual port 2 pins are set as CMOS or NMOS open-drain when 1 is set in PCR. ...
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Function Table 8-6 shows the port 2 functions. Table 8-6 Port 2 Functions Functions Functions and Selection Method The function depends on the corresponding bit in PCR2 PCR2 Function P2 /SO The function depends ...
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Port 3 8.4.1 Overview Port 8-bit I/O port, configured as shown in figure 8-3. 8.4.2 Register Configuration and Description Table 8-8 shows the port 3 register configuration. Table 8-8 Port 3 Registers Name Port data register ...
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Port data register 3 (PDR3) Bit Initial value 0 Read/Write R/W PDR3 is an 8-bit register that stores data for port 3 pins P3 bits are set to 1, the values stored in PDR3 are read, ...
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Port mode register 3 (PMR3) Bit 7 — Initial value 0 Read/Write — PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'04. Bits 7, 6, ...
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Bit 2: P3 /RESO pin function switch (RESO) 2 This bit selects whether pin P3 Bit 2 RESO Description 0 Functions as P3 Functions as RESO output pin 1 Bit 1: P3 /UD pin function switch (UD) 1 This bit ...
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Pin Pin Functions and Selection Method P3 /SCK The pin function depends on bits CKE1, CKE0, and SMR31 in SCR31 and bit 3 31 PCR3 in PCR3. 3 CKE1 CKE0 COM3 PCR3 Pin function P3 /RESO The pin function depends ...
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Pin States Table 8-10 shows the port 3 pin states in each operating mode. Table 8-10 Port 3 Pin States Pins Reset Sleep P3 High- Retains 7 P3 impedance previous 6 P3 /TXD state /RXD 4 ...
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Port 4* Note /IRQ , only chip internal input port 8.5.1 Overview Port 3-bit I/O port and 1-bit input internal port, configured as shown in figure 8- ...
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Port data register 4 (PDR4) Bit 7 — Initial value 1 Read/Write — PDR4 is an 8-bit register that stores data for port 4 pins P4 bits are set to 1, the values stored in PDR4 are read, regardless ...
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Pin Functions Table 8-12 shows the port 4 pin functions. Table 8-12 Port 4 Pin Functions Pin Pin Functions and Selection Method P4 /IRQ The function depends on bit IRQ0 in PMR3 Function P4 /TXD The pin ...
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Pin States Table 8-13 shows the port 4 pin states in each operating mode. Table 8-13 Port 4 Pin States Pins Reset Sleep P4 /IRQ High Retains 3 0 previous state P4 /TXD High - /RXD ...
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Port 5 8.6.1 Overview Port 8-bit I/O port, configured as shown in figure 8-5. 8.6.2 Register Configuration and Description Table 8-14 shows the port 5 register configuration. Table 8-14 Port 5 Registers Name Port data register ...
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Port data register 5 (PDR5) Bit Initial value 0 Read/Write R/W PDR5 is an 8-bit register that stores data for port 5 pins P5 bits are set to 1, the values stored in PDR5 are read, ...
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Port mode register 5 (PMR5) Bit 7 WKP WKP 7 Initial value 0 Read/Write R/W PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit ...
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Pin States Table 8-16 shows the port 5 pin states in each operating mode. Table 8-16 Port 5 Pin States Pins Reset Sleep P5 /WKP to High- Retains WKP P5 impedance previous 0 0 state Note: ...
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Port 6 8.7.1 Overview Port 8-bit I/O port. The port 6 pin configuration is shown in figure 8-6. 8.7.2 Register Configuration and Description Table 8-17 shows the port 6 register configuration. Table 8-17 Port 6 Registers ...
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Port data register 6 (PDR6) Bit Initial value 0 Read/Write R/W PDR6 is an 8-bit register that stores data for port 6 pins P6 If port 6 is read while PCR6 bits are set to 1, ...
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Pin Functions Table 8-18 shows the port 6 pin functions. Table 8-18 Port 6 Pin Functions Pin Pin Functions and Selection Method The pin function depends on bit PCR6 7 0 PCR6 Pin function 8.7.4 Pin ...
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Port 7 8.8.1 Overview Port 8-bit I/O port, configured as shown in figure 8-7. 8.8.2 Register Configuration and Description Table 8-20 shows the port 7 register configuration. Table 8-20 Port 7 Registers Name Port data register ...
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Port data register 7 (PDR7) Bit Initial value 0 Read/Write R/W PDR7 is an 8-bit register that stores data for port 7 pins P7 bits are set to 1, the values stored in PDR7 are read, ...
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Pin Functions Table 8-21 shows the port 7 pin functions. Table 8-21 Port 7 Pin Functions Pin Pin Functions and Selection Method The pin function depends on bit PCR7 7 0 PCR7 Pin function 8.8.4 Pin ...
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Port 8 8.9.1 Overview Port 8-bit I/O port configured as shown in figure 8-8. 8.9.2 Register Configuration and Description Table 8-23 shows the port 8 register configuration. Table 8-23 Port 8 Registers Name Port data register ...
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Port control register 8 (PCR8) Bit 7 PCR8 PCR8 7 Initial value 0 Read/Write W PCR8 is an 8-bit register for controlling whether each of the port 8 pins P8 input or output pin. Setting a PCR8 bit to ...
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Port 9 8.10.1 Overview Port 4-bit I/O port. Figure 8-9 shows its pin configuration. 8.10.2 Register Configuration and Description Table 8-26 shows the port 9 register configuration. Table 8-26 Port 9 Registers Name Port data register ...
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Port data register 9 (PDR9) Bit 7 — Initial value 0 Read/Write — PDR9 is an 8-bit register that stores data for port 9 pins P9 bits are set to 1, the values stored in PDR9 are read, regardless ...
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Pin Functions Table 8-27 shows the port 9 pin functions. Table 8-27 Port 9 Pin Functions Pin Pin Functions and Selection Method The pin function depends on bit PCR9 3 0 PCR9 Pin function 8.10.4 Pin ...
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Port A 8.11.1 Overview Port 4-bit I/O port, configured as shown in figure 8-10. Figure 8-10 Port A Pin Configuration 8.11.2 Register Configuration and Description Table 8-29 shows the port A register configuration. Table 8-29 Port ...
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Port control register A (PCRA) Bit 7 — Initial value 1 Read/Write — PCRA controls whether each of port A pins PA Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit ...
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Port B 8.12.1 Overview Port 8-bit input-only port, configured as shown in figure 8-11. Figure 8-11 Port B Pin Configuration 8.12.2 Register Configuration and Description Table 8-32 shows the port B register configuration. Table 8-32 Port ...
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Input/Output Data Inversion Function 8.13.1 Overview With input pins RXD , and RXD 31 inverted form /TXD 5 P4 /TXD 2 Figure 8.12 Input/Output Data Inversion Function 8.13.2 Register Configuration and Descriptions Table 8.33 ...
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Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. Bit 5: P4 /TXD pin function switch (SPC32 This bit selects whether pin P4 Bit 5 ...
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Bit 1: TXD pin output data inversion switch 31 Bit 1 specifies whether or not TXD Bit 1 SCINV1 Description 0 TXD output data is not inverted 31 1 TXD output data is inverted 31 Bit 0: RXD pin input ...
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Overview The H8/3937 Series and H8/3937R Series provide five timers: timers and a watchdog timer. The functions of these timers are outlined in table 9-1. Table 9-1 Timer Functions Name Functions Timer A 8-bit interval ...
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Timer A 9.2.1 Overview Timer 8-bit timer with interval timing and time-base functions. A clock signal divided from 76.8 kHz (if a 76.8 kHz crystal oscillator is connected), from 160 kHz (if a 160 kHz crystal ...
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Block diagram Figure 9-1 shows a block diagram of timer A. ø W 1/4 ø ø /32 W ø /16 W ø ø TMOW ø/32 ø/16 ø/8 ø/4 ø Notation: TMA: Timer mode ...
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Register configuration Table 9-3 shows the register configuration of timer A. Table 9-3 Timer A Registers Name Timer mode register A Timer counter A Clock stop register 1 Subclock output select register 9.2.2 Register Descriptions 1. Timer mode register ...
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Bits Clock output select (TMA7 to TMA5) Bits choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16 can be output in ...
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Bits Internal clock select (TMA3 to TMA0) Bits select the clock input to TCA. The selection is made as follows. Bit 3 Bit 2 Bit 1 Bit 0 TMA3 TMA2 TMA1 TMA0 0 0 ...
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Timer counter A (TCA) Bit 7 TCA7 Initial value 0 Read/Write R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to ...
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Subclock Output Select Register (CWOSR) Bit — — Initial value Read/Write: — — CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE ...