HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 348

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The host must transition the SS pin from high to low to begin each 32-bit packet. The FLEX
decoder must see a negative transition on the SS pin in order for the host to initiate each packet
communication.
12.2.2
Refer to figure 12-5.When the FLEX decoder has a packet for the host to read, the following
occurs:
1. The FLEX decoder drives the READY pin low.
2. If the FLEX decoder is not already selected, the host selects the FLEX decoder by driving the
3. The host receives (and sends) a 32-bit packet.
4. The host de-selects the FLEX decoder by driving the SS pin high (optional).
When the host is reading a packet from the FLEX decoder, it must send a valid packet to the
FLEX decoder. If the host has no data to send, it is suggested that the host send a Checksum
Packet with all of the data bits set to 0 in order to avoid disabling the FLEX decoder. See 12.3.1,
Checksum Packet for more details on enabling and disabling the FLEX decoder.
The following figure illustrates that it is not necessary to de-select the FLEX decoder between
packets when the packets are initiated by the FLEX decoder.
334
READY
MOSI
MISO
SCK
SS pin low.
Figure 12-5 Typical Multiple Packet Communications Initiated by the FLEX decoder
SS
Packet Communication Initiated by the FLEX decoder
1
2
3
D31
D31
D1 D0
D1 D0
4
High impedance state
D31
D31
D1 D0
D1 D0
D31
D31
D1 D0
D1 D0