HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 310

MCU 3/5V 60K 100-TQFP

HD6473937RXV

Manufacturer Part Number
HD6473937RXV
Description
MCU 3/5V 60K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheet

Specifications of HD6473937RXV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
59
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473937RXV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
c. Data transfer operations
Data transfer on SCI3 first of all requires that SCI3 be initialized as described in “SCI
initialization” under 10.3.3, 2. c. Data transfer operations, and shown in figure 10-7.
Figure 10-13 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
296
SCI3 initialization
Transmitting
Figure 10-13 Example of Data Transmission Flowchart (Synchronous Mode)
1
2
Sets bits SPC31 and
SPC32 to 1 in SPCR
Clear bit TE to 0
Read bit TDRE
Read bit TEND
Write transmit
Continue data
transmission?
data to TDR
TDRE = 1?
TEND = 1?
in SCR3
in SSR
in SSR
Start
End
Yes
No
Yes
No
Yes
No
1.
2.
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.

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