HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 352

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.2.4
The following table describes the packet ID’s for all of the packets that can be sent to the host
from the FLEX decoder.
Table 12-2 Decoder-to-Host Packet ID Map
Packet ID (Hexadecimal)
00
01
02- 57
58 - 5F
60
61 - 7D
7E
7F
80 - FE
FF
12.3
The following sections describe the packets of information sent from the host to the FLEX
decoder. In all cases the packets should be sent MSB first (bit 7 of byte 3 = bit 31 of the packet =
MSB).
12.3.1
The Checksum Packet is used to insure proper communication between the host and the FLEX
decoder. The FLEX decoder exclusive-or’s the 24 data bits of every packet it receives (except the
Checksum Packet and the special packet ID’s 1C through 1F hexadecimal) with an internal
checksum register. Upon reset and whenever the host writes a packet to the FLEX decoder, the
FLEX decoder is disabled from sending any information to the host processor until the host
processor sends a Checksum Packet with the proper checksum value (CV) to the FLEX decoder.
When the FLEX decoder is disabled in this way, it prompts the host to read the Part ID Packet.
Note that all other operation continues normally when the FLEX decoder is “disabled”. Disabled
only implies that data cannot be read, all other internal operations continue to function.
When the FLEX decoder is reset, it is disabled and the internal checksum register is initialized to
the 24 bit part ID defined in the Part ID Packet. See 12.4.8, Part ID Packet for a description of the
Part ID. Every time a packet other than the Checksum Packet and the special packets 1C through
338
Decoder-to-Host Packet Map
Host-to-Decoder Packet Descriptions
Checksum Packet
Packet Type
Block Information Word
Address
Vector or Message (ID is word number in frame)
Reserved
Roaming Status Packet
Reserved
Receiver Shutdown
Status
Reserved
Part ID