HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 431

MCU 3/5V 60K 100-TQFP

HD6473937RXV

Manufacturer Part Number
HD6473937RXV
Description
MCU 3/5V 60K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheet

Specifications of HD6473937RXV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
59
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473937RXV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
A.3
The tables here can be used to calculate the number of states required for instruction execution.
Table A-4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A-3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A-4:
I = L = 2,
From table A-3:
S
Number of states required for execution = 2
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A-4:
I = 2,
From table A-3:
S
Number of states required for execution = 2
Table A-3
Execution Status
(instruction cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note:
I
I
= 2,
= S
J
= S
*
J = K = 1,
S
Number of Execution States
K
L
Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.
= 2
J = K = M = N= 0
= 2
Number of Cycles in Each Instruction
L = M = N = 0
S
I
+ J S
S
S
S
S
S
S
I
J
K
L
M
N
J
+ K S
Access Location
On-Chip Memory
2
1
K
+ L S
2 + 2 2 = 8
2 + 1 2+ 1 2 = 8
L
+ M S
M
+ N S
On-Chip Peripheral Module
2 or 3*
1
N
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