HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 119

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.3
5.3.1
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock supply from the clock pulse generator is halted, so
the CPU and peripheral modules other than the FLEX™ decoder stop functioning, but as long as
the specified voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip
peripheral module registers are retained. On-chip RAM contents will be further retained down to a
minimum RAM data retention voltage. The I/O ports go to the high-impedance state.
5.3.2
Standby mode is cleared by an interrupt (IRQ
pin.
When an interrupt is requested, the system clock pulse generator starts. After the time set in bits
STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip,
standby mode is cleared, and interrupt exception handling starts. Operation resumes in active
(high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1.
Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since
system clock signals are supplied to the entire chip as soon as the system clock pulse generator
starts functioning, the RES pin should be kept at the low level until the pulse generator output
stabilizes.
5.3.3
Bits STS2 to STS0 in SYSCR1 should be set as follows.
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time at least as long as the oscillation settling time.
Clearing by interrupt
Clearing by RES input
When a crystal oscillator is used
Standby Mode
Transition to Standby Mode
Clearing Standby Mode
Oscillator Settling Time after Standby Mode is Cleared
1
or IRQ
0
), WKP
7
to WKP
0
or by input at the RES
105