HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 13

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.4 Interrupts............................................................................................................................ 323
11.5 Typical Use........................................................................................................................ 323
11.6 Application Notes.............................................................................................................. 327
Section 12 FLEX™ Roaming Decoder II
12.1 Overview............................................................................................................................ 329
12.2 SPI Packets ........................................................................................................................... 333
12.3 Host-to-Decoder Packet Descriptions................................................................................ 338
12.4 Decoder-to-Host Packet Descriptions................................................................................ 358
12.5 Application Notes.............................................................................................................. 374
12.6 Timing Diagrams (Reference Data) .................................................................................. 387
12.1.1 Features ................................................................................................................ 329
12.1.2 System Block Diagram......................................................................................... 330
12.1.3 Functional Block Diagram ................................................................................... 332
12.2.1 Packet Communication Initiated by the Host....................................................... 333
12.2.2 Packet Communication Initiated by the FLEX decoder....................................... 334
12.2.3 Host-to-Decoder Packet Map ............................................................................... 336
12.2.4 Decoder-to-Host Packet Map ............................................................................... 338
12.3.1 Checksum Packet.................................................................................................. 338
12.3.2 Configuration Packet............................................................................................ 341
12.3.3 Control Packet ...................................................................................................... 344
12.3.4 All Frame Mode Packet........................................................................................ 345
12.3.5 Operator Messaging Address Enable Packet........................................................ 347
12.3.6 Roaming Control Packet ...................................................................................... 347
12.3.7 Timing Control Packet.......................................................................................... 350
12.3.8 Receiver Line Control Packet .............................................................................. 351
12.3.9 Receiver Control Configuration Packets.............................................................. 351
12.3.10 Frame Assignment Packets .................................................................................. 355
12.3.11 User Address Enable Packet ................................................................................ 356
12.3.12 User Address Assignment Packets ....................................................................... 357
12.4.1 Block Information Word Packet .......................................................................... 359
12.4.2 Address Packet ..................................................................................................... 360
12.4.3 Vector Packet........................................................................................................ 361
12.4.4 Message Packet .................................................................................................... 366
12.4.5 Roaming Status Packet ......................................................................................... 366
12.4.6 Receiver Shutdown Packet ................................................................................... 369
12.4.7 Status Packet ........................................................................................................ 370
12.4.8 Part ID Packet....................................................................................................... 372
12.5.1 Receiver Control .................................................................................................. 374
12.5.2 Message Building ................................................................................................. 377
12.5.3 Building a Fragmented Message .......................................................................... 379
12.5.4 Operation of a Temporary Address ...................................................................... 382
12.5.5 Using the Receiver Shutdown Packet .................................................................. 384
..................................................................... 329
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