HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 359

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MTC: Minute Timer Clear. Setting this bit will cause the one minute timer to restart from 0.
EAE: End of Addresses Enable. When this bit is set, the EA bit in the Status Packet will be set
immediately after the FLEX decoder decodes the last address word in the frame if any of the
enabled FLEX decoder addresses was detected in the frame. When this bit is cleared, the EA bit
will never be set.
ON: Turn On Decoder. Set if the FLEX decoder should be decoding FLEX signals. Clear if signal
processing should be off (very low power mode). If the ON bit is changed twice and the control
packets making the changes are received within 2ms of each other, the FLEX decoder may ignore
the double change and stay in its original state (e.g. if it is turned off then on again within 2ms it
may stay on and ignore the off pulse). Therefore it is recommended that the host insures a
minimum of 2ms between changes in the ON bit. (value after reset=0)
Note: Turning off the FLEX decoder must be done using the following sequence. This sequence
Timing between these steps is specified below and is measured from the positive edge of the last
clock of one packet to the positive edge of the last clock of the next packet:
12.3.4
The All Frame Mode Packet is used to decrement temporary address enable counters by one,
decrement the all frame mode counter by one, and/or enable or disable forcing all frame mode. All
frame mode is enabled if any temporary address enable counter is non-zero, the all frame mode
counter is non-zero, or the force all frame mode bit is set. If all frame mode is enabled, the FLEX
decoder will attempt to decode every frame and send a Status Packet with the EOF (end-of-frame)
bit set at the end of every frame. Both the all frame mode counter and the temporary address
enable counters can only be incremented internally by the FLEX decoder and can only be
decremented by the host. The FLEX decoder will increment a temporary address enable counter
whenever a short instruction vector is received assigning the corresponding temporary address.
The minimum time between steps 1 and 2 is 2ms or the programmed shut down time,
whichever is greater. The programmed shut down time is the sum of all the of the times
programmed in the used Receiver Shut Down Settings Packets.
There is no maximum time between steps 1 and 2.
The minimum time between steps 2 and 3 is 2ms.
The maximum time between steps 2 and 3 is the programmed warm up time minus 2ms.
The programmed warm up time is the sum of all the of the times programmed in the used
Receiver Warm Up Settings Packets.
is performed automatically by the FLEXstack software version 1.2 and greater.
3. Turn off the FLEX decoder by sending a Control Packer with the ON bit cleared.
1. Turn off the FLEX decoder by sending a Control Packer with the ON bit cleared.
2. Turn on the FLEX decoder by sending a Control Packer with the ON bit set.
All Frame Mode Packet
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