HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 263

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4. Serial data register L (SDRL)
SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits).
In 8-bit transfer, the data written into SDRL is output from the SO
replacement process, data is input LSB-first from the SI
LSB direction.
The operation in 16-bit transfer is the same as for 8-bit transfer, except that the input data is taken
from SDRU.
SDRL read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRL is undefined upon reset.
5. Clock stop register 1 (CKSTPR1)
Bit
Initial value
Read/Write
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to SCI1 is described here. For details of the other bits, see the
sections on the relevant modules.
Bit
Initial value
Read/Write
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Undefined
R/W
SDRL7
7
1
R/W
7
Undefined
R/W
SDRL6
R/W
6
1
6
Undefined
SDRL5
R/W
R/W
5
1
5
Undefined
SDRL4
R/W
R/W
4
1
4
1
, and the data is shifted in the MSB
Undefined
SDRL3
R/W
R/W
3
3
1
1
Undefined
in LSB-first order. In the
SDRL2
R/W
R/W
2
2
1
Undefined
SDRL1
R/W
R/W
1
1
1
Undefined
SDRL0
R/W
0
R/W
0
1
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