HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 109

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.1
The H8/3937 Series and H8/3937R Series have nine modes of operation after a reset. These
include eight power-down modes, in which power dissipation is significantly reduced. Table 5-1
gives a summary of the eight operating modes.
Table 5-1
Operating Mode
Active (high-speed) mode
Active (medium-speed) mode
Subactive mode
Sleep (high-speed) mode
Sleep (medium-speed) mode
Subsleep mode
Watch mode
Standby mode
Module standby mode
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal
states in each mode.
Overview
Operating Modes
Section 5 Power-Down Modes
Description
The CPU and all on-chip peripheral functions are operable on the
system clock in high-speed operation. The FLEX™ decoder is
independently operable on the subclock.
The CPU and all on-chip peripheral functions are operable on the
system clock in low-speed operation. The FLEX™ decoder is
independently operable on the subclock.
The CPU is operable on the subclock in low-speed operation. The
FLEX™ decoder is independently operable on the subclock.
The CPU halts. On-chip peripheral functions are operable on the
system clock. The FLEX™ decoder is independently operable on
the subclock.
The CPU halts. On-chip peripheral functions operate at a
frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock frequency.
The FLEX™ decoder is independently operable on the subclock.
The CPU halts. Timer A, timer C, timer G, timer F, the WDT, SCI1,
SCI31, SCI32, and the FLEX™ decoder are operable on the
subclock.
The timer A time-base function, timer F, timer G, and the FLEX™
decoder are operable on the subclock.
The CPU and all on-chip peripheral functions halt. The FLEX™
decoder is independently operable on the subclock.
Individual on-chip peripheral functions specified by software enter
standby mode and halt.
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