HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 284

MCU 3/5V 60K 100-TQFP

HD6473937RXV

Manufacturer Part Number
HD6473937RXV
Description
MCU 3/5V 60K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheet

Specifications of HD6473937RXV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
59
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473937RXV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 2: Transmit end (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
0
1
Bit 1: Multiprocessor bit receive (MPBR)
Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in
asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1
MPBR
0
1
Note:
Bit 0: Multiprocessor bit transfer (MPBT)
Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous
mode. The bit MPBT setting is invalid when synchronous mode is selected, when the
multiprocessor communication function is disabled, and when not transmitting.
Bit 0
MPBT
0
1
270
*
When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
affected and retains its previous state.
Description
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
Transmission ended
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is
sent
Description
Data in which the multiprocessor bit is 0 has been received*
Data in which the multiprocessor bit is 1 has been received
Description
A 0 multiprocessor bit is transmitted
A 1 multiprocessor bit is transmitted
(initial value)
(initial value)
(initial value)

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