HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 279

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 4: Receive enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
0
1
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
Bit 3: Multiprocessor interrupt enable (MPIE)
Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is
only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR
set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3
MPIE
0
1
Note:
2. In this state, serial data reception is started when a start bit is detected in asynchronous
*
cleared to 0, and retain their previous state.
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Receive data transfer from RSR to RDR, receive error detection, and setting of the
RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of
the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor
bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is
received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI
and ERI requests (when bits TIE and RIE in serial control register 3 (SCR3) are set to
1) and setting of the RDRF, FER, and OER flags are enabled.
Description
Receive operation disabled*
Receive operation enabled*
Description
Multiprocessor interrupt request disabled (normal receive operation)
Clearing conditions:
When data is received in which the multiprocessor bit is set to 1
Multiprocessor interrupt request enabled*
2
1
(RXD pin is receive data pin)
(RXD pin is I/O port)
(initial value)
(initial value)
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