HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 278

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 7: Transmit interrupt enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE
0
1
Bit 6: Receive interrupt enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing
bit RIE to 0.
Bit 6
RIE
0
1
Bit 5: Transmit enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
0
1
Notes: 1. Bit TDRE in SSR is fixed at 1.
264
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC31 or SPC32 in SPCR, to decide the transmission format
before setting bit TE to 1.
Description
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
Description
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
Description
Transmit operation disabled*
Transmit operation enabled*
2
1
(TXD pin is transmit data pin)
(TXD pin is I/O port)
(initial value)
(initial value)
(initial value)