HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 201

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2. Time base operation
When bit TMA3 in TMA is set to 1, timer A functions as a time base by counting clock signals
output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA.
A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1
clears both TCA and prescaler W to their initial values of H'00.
3. Clock output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin
TMOW. Nine different clock output signals can be selected by means of bits TMA7 to TMA5 in
TMA and bit CWOS in CWOSR. The system clock divided by 32, 16, 8, or 4 can be output in
active mode and sleep mode. A ø
sleep mode, watch mode, subactive mode, and subsleep mode. The ø
except the reset state.
9.2.4
Table 9-4 summarizes the timer A operation states.
Table 9-4
Operation Mode
TCA
TMA
Note: When the time base function is selected as the internal clock of TCA in active mode or
9.2.5
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
Interval
Time base
sleep mode, the internal clock is not synchronous with the system clock, so it is
synchronized by a synchronizing circuit. This may result in a maximum error of 1/ø (s) in the
count cycle.
Timer A Operation States
Application Note
Timer A Operation States
Reset Active
Reset Functions Functions Halted
Reset Functions Functions Functions Functions Functions Halted
Reset Functions Retained Retained Functions Retained Retained Retained
w
signal divided by 32, 16, 8, or 4 can be output in active mode,
Sleep
Watch
Sub-
active
Halted
w
Sub-
sleep
Halted
clock is output in all modes
Standby
Halted
Module
Standby
Halted
Halted
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