HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 372

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4
The following sections describe the packets of information that will be sent from the FLEX
decoder to the host. In all cases the packets are sent MSB first (bit 7 of byte 3 = bit 31 of the
packet = MSB). The FLEX decoder decides what data should be sent to the host. If the FLEX
decoder is disabled through the checksum feature (see 12.3.1, Checksum Packet for a description
of the checksum feature) the Part ID Packet will be sent. Data Packets relating to data received
over the air are buffered in the 32 packet transmit buffer. The Data packets include Block
Information Word Packets, Address Packets, Vector Packets, and Message Packets.
If the FLEX decoder is enabled and a receiver shutdown packet is pending, the receiver shutdown
packet will be sent. If there is no receiver shutdown packet pending, but there is a roaming status
packet pending, the roaming status packet will be sent. If neither the receiver shutdown packet nor
the roaming status packet is pending and there is data in the transmit buffer, a packet from the
transmit buffer will be sent. Otherwise, the FLEX decoder will send the Status Packet (which is
not buffered). In the event of a buffer overflow, the FLEX decoder will automatically stop
decoding and clear the buffer.
It is recommended that the Host be designed to empty the FIFO buffer every block with enough
time left over to read a status packet. This would ensure that any applicable Status Packet would
be received within 1 block of the new status being available.
358
Receiver Shutdown Register
Roaming Status Register
FIFO Transmit Buffer
32 32 Data Packet
Part ID Register
Decoder-to-Host Packet Descriptions
Status Register
Figure 12-8 FLEX decoder SPI Transmit Functional Block Diagram
32
32
32
32
32
32
SPI Transmit Register
MISO