HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 69

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2. Bit manipulation in a register containing a write-only bit
Example 3: BCLR instruction executed designating port 3 control register PCR3
As in the examples above, P3
high-level signal at P3
signals. In this example, the BCLR instruction is used to change pin P3
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
Input/output
Pin state
PCR3
PDR3
[B: BCLR instruction executed]
BSET
[C: After executing BCLR]
Input/output
Pin state
PCR3
PDR3
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR3 becomes 0, making P3
and 6 in PCR3 change to 1, so that P3
#0
P3
Input
Low
level
0
1
P3
Output
Low
level
1
1
,
7
7
6
. The remaining pins, P3
@PCR3
P3
Input
High
level
0
0
P3
Output
High
level
1
0
7
and P3
6
6
6
7
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
are input pins, with a low-level signal input at P3
and P3
The BCLR instruction is executed designating PCR3.
5
5
6
change from input pins to output pins.
5
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
to P3
4
4
0
, are output pins that output low-level
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
3
3
0
an input port. However, bits 7
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
0
2
2
to an input port. It is
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
1
1
7
and a
P3
Output
Low
level
1
0
P3
Input
High
level
0
0
0
0
55