HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 365

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.3.8
This packet gives the host control over the settings on the receiver control lines (S0-S7) in all
modes except reset. In reset, the receiver control lines are in high impedance settings. The ID for
the Receiver Line Control Packet is 15 (decimal).
Table 12-10 Receiver Line Control Packet Bit Assignments
Byte 3
Byte 2
Byte 1
Byte 0
FRS: Force Receiver Setting. Setting a bit to one will cause the corresponding CLS bit in this
packet to override the internal receiver control settings on the corresponding receiver control line
(S0-S7). Clearing a bit gives control of the corresponding receiver control lines (S0-S7) back to
the FLEX decoder.(value after reset=0)
CLS: Control Line Setting. If the corresponding FRS bit was set in this packet, these bits define
what setting should be applied to the corresponding receiver control lines.(value after reset=0)
12.3.9
These packets allow the host to configure what setting is applied to the receiver control lines S0-
S7, how long to apply the setting, and when to read the value of the LOBAT input pin. For a more
detailed description of how the FLEX decoder uses these settings see 12.5.1, Receiver Control.
The FLEX decoder defines 12 different receiver control settings. Proper operation is not
guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control
Packet is set). The IDs for these packets range from 16 to 27 (decimal).
1. Receiver Off Setting Packet
Table 12-11 Receiver Off Setting Packet Bit Assignments
Byte 3
Byte 2
Byte 1
Byte 0
Bit 7
0
0
FRS
CLS
Bit 7
0
0
CLS
ST
Receiver Line Control Packet
Receiver Control Configuration Packets
7
7
7
7
Bit 6
0
0
FRS
CLS
Bit 6
0
0
CLS
ST
6
6
6
6
Bit 5
0
0
FRS
CLS
Bit 5
0
0
CLS
ST
5
5
5
5
Bit 4
0
0
FRS
CLS
Bit 4
1
0
CLS
ST
4
4
4
4
Bit 3
1
0
FRS
CLS
Bit 3
0
LBC
CLS
ST
3
3
3
3
Bit 2
1
0
FRS
CLS
Bit 2
0
0
CLS
ST
2
2
2
2
Bit 1
1
0
FRS
CLS
Bit 1
0
0
CLS
ST
1
1
1
1
Bit 0
1
0
FRS
CLS
Bit 0
0
0
CLS
ST
0
0
0
0
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