HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 129

MCU 3/5V 60K 100-TQFP

HD6473937RXV

Manufacturer Part Number
HD6473937RXV
Description
MCU 3/5V 60K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheet

Specifications of HD6473937RXV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
59
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473937RXV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) 16t
Notation:
t
t
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) 8t
Notation:
t
t
t
t
osc
cyc
osc
w
cyc
subcyc
:
:
:
:
:
:
OSC clock cycle time
System clock (ø) cycle time
CPU operating clock)
øw/8 is selected as the CPU operating clock, and wait time = 8192 states)
OSC clock cycle time
Watch clock cycle time
System clock (ø) cycle time
Subclock (ø
SUB
processing states) }
exception handling execution states) (t
processing states) }
to STS0) + (number of interrupt exception handling execution states) }
(t
) cycle time
cyc
after transition)
w
(t
(t
osc
+ (8192 + 14) 2t
cyc
subcyc
+ 14 2t
before transition) + (number of interrupt
before transition) + { (wait time set in STS2
osc
= 76t
cyc
osc
osc
after transition)
= 24t
(when ø/8 is selected as the
.................................. (2)
w
+ 16412t
........................ (3)
osc
(when
115

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