HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 379

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4. Short Instruction Vector
Table 12-24 Short Instruction Vector Packet Bit Assignments
Byte 3
Byte 2
Byte 1
Byte 0
V: 001 for a Short Instruction Vector
WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the
frame.
e: Set if more than 2 bit errors are detected in the word or, if after error correction, the check
character calculation fails.
p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d)
d: Data bits whose definition depend on the i bits in this packet according to the following table.
Note that if this vector is received on a long address and the e bit in this packet is not set, the
decoder will send a Message Packet immediately following the Vector Packet. All message bits in
the message packet are unused and should be ignored for all modes except the Temporary address
assignment with MSN (i
Notes: 1. Assigned temporary address (a) and assigned frame (f). See 12.5.4, Operation of a
i
0
0
0
0
1
1
1
1
2
i
0
0
1
1
0
0
1
1
1
I
0
1
0
1
0
1
0
1
2. Assigned temporary address (a), MSb of assigned frame (f
0
Bit 7
0
e
x
d
4
Temporary Address for a description of the use of these fields.
number (N). The message packet sent with this instruction on long addresses contains
extra frame information, see 12.5.4, Operation of a Temporary Address for a description
and for details on the use of the other fields.
d
a
d
a
3
10
3
10
d
a
d
a
2
9
2
9
d
a
d
a
1
8
1
8
Bit 6
WN
p
x
d
1
3
d
a
d
a
0
7
0
7
2
6
i
1
d
f
d
f
6
6
i
6
6
0
=010).
d
f
d
N
5
Bit 5
WN
p
d
d
5
5
5
0
10
2
d
f
d
N
4
5
4
4
4
d
f
d
N
3
3
3
3
d
f
d
N
2
2
2
Bit 4
WN
x
d
d
2
9
1
d
f
d
N
1
1
1
4
1
d
f
d
N
0
0
0
0
Description
Temporary address assignment*
11 Event Flags for System Event
Temporary address assignment with MSN*
Reserved
Reserved
Reserved
Reserved
Reserved for test
Bit 3
WN
x
d
d
8
0
3
Bit 2
WN
V
d
i
2
7
2
6
2
), and message sequence
Bit 1
WN
V
d
i
1
1
6
1
1
Bit 0
WN
V
d
i
0
5
0
0
365
2