HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 388

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.5
12.5.1
Introduction: The FLEX decoder has 8 programmable receiver control lines (S0-S7). The host
has control of the receiver warm up and shut down timing as well as all of the various settings on
the control lines through configuration registers on the FLEX decoder. The configuration registers
for most settings allow the host to configure what setting is applied to the control lines, how long
to apply the setting, and if the LOBAT input pin is polled before changing from the setting. With
this programmability, the FLEX decoder should be able to interface with many off-the-shelf
receiver ICs. When using the internal demodulator (i.e. when the IDE bit of the configuration
packet is set), the S0 pin becomes the input for the demodulator and the S0 register setting in the
receiver control configuration packets controls the tracking mode of the peak and valley detectors
for the internal data slicer. When the S0 bit is set in a receiver setting, the internal data slicer will
be in fast track mode. When the S0 bit is cleared in a receiver setting, the internal data slicer will
be in slow track mode. For details on the configuration of the receiver control settings, see 12.3.9,
Receiver Control Configuration Packets.
1. Receiver Settings at Reset
The receiver control ports are three-state outputs which are set to the high-impedance state when
the FLEX decoder is reset and until the corresponding FRS bit in the Receiver Line Control Packet
is set or until the FLEX decoder is turned on by setting the ON bit in the Control Packet. This
allows the designer to force the receiver control lines to the receiver off setting with external pull-
up or pull-down resistors before the host can configure these settings in the FLEX decoder. When
the FLEX decoder is turned on, the receiver control ports are driven to the settings configured by
the “12.3.9 Receiver Control Configuration Packets” until the FLEX decoder is reset again.
2. Automatic Receiver Warm Up Sequence
The FLEX decoder allows for up to 6 steps associated with warming up the receiver. When the
FLEX decoder automatically turns on the receiver, it starts the warm up sequence 160 ms before it
requires valid signals at the EXTS0 and EXTS1 input pins (or the equivalent internal signals when
using the internal demodulator/data slicer). The first step of the warm up sequence involves
leaving the receiver control lines in the “Off” state for the amount of time programmed for “Warm
Up Off Time”. At the end of the “Warm Up Off Time”, the first warm up setting, if enabled, is
applied to the receiver control lines for the amount of time programmed for that setting. Each
subsequent warm up setting is applied to the receiver control lines for their corresponding time
until a disabled warm up setting is found. At the end of the last used warm up setting, the
“1600sps Sync Setting” or the “3200sps Sync Setting” is applied to the receiver control lines
depending on the current state of the FLEX decoder. The sum total of all of the used warm up
times and the “Warm Up Off Time” must not exceed 160ms. If it exceeds 160ms, the FLEX
decoder will execute the receiver shut down sequence at the end of the 160ms warm up period.
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Application Notes
Receiver Control