HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 117

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.2
5.2.1
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON
bits in SYSCR2 are also cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in
sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are
operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and
MA0 bits in SYSCR1. CPU register contents are retained.
The CPU may operate at a 1/2 state faster timing at transition to sleep (medium-speed) mode.
5.2.2
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous counter,
IRQ
pin.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A
transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the
condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt
enable register.
To synchronize the interrupt request signal with the system clock, up to 2/ø (s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
Clearing by interrupt
Clearing by RES input
4
to IRQ
Sleep Mode
Transition to Sleep Mode
Clearing Sleep Mode
0
, WKP
7
to WKP
0
, SCI1, SCI31, SCI32, or A/D converter), or by input at the RES
103