HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 369

• Manufacturer Part Number: HD6473937RXV
• Description: MCU 3/5V 60K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD6473937RXV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 59
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

ST: Step Time. This is the time the FLEX decoder is to wait before applying the next state’s
receiver control value to the receiver control lines. The setting is in steps of 625 s. Valid values
are 625 s (ST=01) to 39.375ms (ST=3F in hexadecimal). (value after reset=625 s)
12.3.10 Frame Assignment Packets
The FLEX protocol defines that each address of a FLEX pager is assigned a home frame and a
battery cycle. The FLEX decoder must be configured so that a frame that is assigned by one or
more of the addresses’ home frames and battery cycles has its corresponding configuration bit set.
For example, if the FLEX decoder has one enabled address and it is assigned to frame 3 with a
battery cycle of 4, the AF bits for frames 3, 19, 35, 51, 67, 83, 99, and 115 should be set and the
AF bits for all other frames should be cleared.
When the FLEX decoder is configured for manual collapse mode by setting the MCM bit in the
Roaming Control Packet, the FLEX decoder will not apply the received system collapse to the AF
bits. The host should set the AF bits for all frames that should be decoded on all channels. For
example, if frames 0 and 64 should be decoded on one channel and frames 4, 36, 68, and 100
should be decoded on another channel, all six of the corresponding AF bits should be set. The host
can then change the receiver’s carrier frequency after the FLEX decoder decodes frames 0, 36, 64,
and 100.
There are 8 Frame Assignment Packets. The Packet IDs for these packets range from 32 to 39
(decimal).
Table 12-16 Frame Assignment Packet Bit Assignments
Byte 3
Byte 2
Byte 1
Byte 0
f: Frame range. This value determines which 16 frames correspond to the 16 AF bits in the packet
according to the following table. At least one of these bits must be set when the FLEX decoder is
turned on by setting the ON bit in the control packet. (value after reset=0)
Bit 7
0
0
AF
AF
15
7
Bit 6
0
0
AF
AF
14
6
Bit 5
1
0
AF
AF
13
5
Bit 4
0
0
AF
AF
12
4
Bit 3
0
0
AF
AF
11
3
Bit 2
f
0
AF
AF
2
10
2
Bit 1
f
0
AF
AF
1
9
1
Bit 0
f
0
AF
AF
0
8
0
355