EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 107

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 5–4. Output Cascading Feature for FIR Structures
Altera Corporation
October 2007
Input
Data
Half DSP Block
144
To support single-channel type FIR filters efficiently, you can configure
one of the multiplier input’s registers to form a tap delay line input,
saving resources and providing higher system performance.
Also shown in
(RSU). This unit provides a rich set of commonly found arithmetic round
and saturation functions used in signal processing.
In addition to the independent multipliers and sum modes, you can use
the DSP blocks to perform shift operations. The DSP block can
dynamically switch between logical shift left/right, arithmetic shift
left/right, and rotation operation in one clock cycle.
A top-level view of the Stratix III DSP block is shown in
A more detailed diagram is shown in
Figure 5–4
is the optional Rounding and Saturation Unit
From Previous Half-Block DSP
Stratix III Device Handbook, Volume 1
+
Figure
To Next
Half-Block
DSP
44
DSP Blocks in Stratix III Devices
44
5–6.
Figure
5–5.
44
Result
5–7