EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 203

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–37. PLL Reconfiguration Scan Chain
Notes to
(1)
(2)
(3)
Altera Corporation
November 2007
scandata
scanclk
scanclkena
configupdate
Table 6–15. Real-Time PLL Reconfiguration Ports (Part 1 of 2)
scanclkena
The Stratix III Left/Right PLLs support
i = 6 or i = 9.
This figure shows the corresponding scan register for the K counter in between the scan registers for the charge
pump and loop filter. The K counter is physically located after the VCO.
PLL Port Name
configupdate
scandataout
scandone
scandata
Figure
inclk
scanclk
6–37:
from m counter
from n counter
/Ci (2)
Serial input data stream to scan
chain.
Serial clock input signal. This
clock can be free running.
Enables
the
the scan chain. Active high
Writes the data in the scan chain
to the PLL. Active high
scandata
1
Table 6–15
logic device (PLD) logic array or I/O pins.
/Ci-1
scanclk
Description
The counter settings are updated synchronously to the clock
frequency of the individual counters. Therefore, all counters are
not updated simultaneously.
to be loaded in
C0 - C6
shows how these signals can be driven by the programmable
and allows
PFD
counters.
/C2
Logic array or I/O pin
GCLK/RCLK or I/O
pins
Logic array or I/O pin
Logic array or I/O pin
LF/K/CP (3)
Clock Networks and PLLs in Stratix III Devices
/C1
Source
Stratix III Device Handbook, Volume 1
/C0
VCO
/m
circuit
PLL reconfiguration
circuit
circuit
circuit
PLL reconfiguration
PLL reconfiguration
PLL reconfiguration
Destination
/n
6–53