EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 527

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Note to
(1)
EP3SL110
EP3SL150
EP3SL200
EP3SE260
EP3SL340
EP3SE50
EP3SE80
EP3SE110
f
f
f
t
t
f
f
t
t
t
t
t
IN
INPFD
VCO
EINDUTY
INCCJ
OUT
OUT_EXT
OUTDUTY
OUTPJ_DC
OUTPJ_IO
FCOMP
CONFIGPLL
Table 1–17. Stratix III Clock Tree Performance (Part 2 of 2)
Table 1–18. Stratix III PLL Specifications (Part 1 of 2)
Symbol
Device
Device is not offered in -2 Speed Grade.
Table
1–17:
Input clock frequency
Input frequency to the PFD
PLL VCO operating range
Input clock or external feedback clock input duty cycle
Input clock cycle to cycle jitter
Output frequency for internal global or regional clock
Output frequency for external clock output
Duty cycle for external clock output (when set to 50%)
Period jitter for dedicated clock output
Period jitter for clock output on regular I/O
External feedback clock compensation time
Time required to reconfigure PLL scan chain
V
C C L
-2 Speed
Grade
600
600
600
600
600
600
(1)
(1)
= 1.1V
PLL Specifications
Table 1–18
both the commercial junction temperature range (0 to 85° C) and the
industrial junction temperature range (-40 to 100° C). Refer to the figure
in “PLL Specifications” in
V
C C L
-3 Speed
Grade
500
500
500
500
500
500
500
500
= 1.1V
Parameter
describes the Stratix III PLL specifications when operating in
Stratix III Device Datasheet: DC and Switching Characteristics
V
C C L
-4 Speed
Grade
450
450
450
450
450
450
450
450
= 1.1V
Table 1–206
V
Stratix III Device Handbook, Volume 2
C C L
for PLL block diagram.
450
450
450
450
450
450
450
450
= 1.1V
-4L Speed
Min
600
40
45
—
—
—
—
—
—
—
5
5
Grade
V
Typ
50
(3)
—
—
—
—
—
—
—
—
—
—
C C L
375
375
375
375
375
375
375
375
= 0.9V
720
717
717
1300
Max
325
Preliminary
60
(3)
55
(3)
(3)
(3)
—
(1)
(2)
(2)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
scanclk cycles
1–15
Preliminary
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
ns
—
%
%