EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 92

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Modes
Figure 4–14. Stratix III Shift-Register Memory Configuration
4–18
Stratix III Device Handbook, Volume 1
w × m × n Shift Register
W
W
W
W
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
Figure 4–14
ROM Mode
All Stratix III TriMatrix memory blocks support ROM mode. A memory
initialization file (.mif) initializes the ROM contents of these blocks. The
address lines of the ROM are registered on M9K and M144K blocks, but
can be unregistered on MLABs. The outputs can be registered or
unregistered. Output registers can be asynchronously cleared. The ROM
read operation is identical to the read operation in the single-port RAM
configuration.
shows the TriMatrix memory block in shift-register mode.
W
W
W
W
Altera Corporation
November 2007
n Number of Taps