EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 238

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III I/O Structure
7–20
Stratix III Device Handbook, Volume 1
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has a
high-capacitive loading. Altera recommends performing IBIS or SPICE
simulations to determine the right slew rate setting for your specific
application.
Programmable Delay
Programmable IOE Delay
The Stratix III device IOE includes programmable delays shown in
Figure 7–8
times, or increase clock-to-output times. Each pin can have a different
input delay from pin to input register or a delay from the output register
to the output pin values to ensure that the bus has the same delay going
into or out of the device. This feature helps read and time margins as it
minimizes the uncertainties between signals in the bus.
1
Programmable Output Buffer Delay
Stratix III devices support delay chains built inside the single-ended
output buffer, as shown in
independently control the rising and falling edge delays of the output
buffer, providing the ability to adjust the output-buffer duty cycle,
compensate channel-to-channel skew, reduce simultaneous switching
output (SSO) noise by deliberately introducing channel-to-channel skew,
and improve high-speed memory-interface timing margins. Stratix III
devices support four levels of output buffer delay settings. The default
setting is No Delay.
1
Open-Drain Output
Stratix III devices provide an optional open-drain output (equivalent to
an open-collector output) for each I/O pin. When configured as
open-drain, the logic value of the output is either high-Z or 0. Typically,
an external pull-up resistor is needed to provide logic high.
Refer to the
chapter in volume 2 of the Stratix III Device Handbook for the
programmable IOE delay specifications.
Refer to the
chapter in volume 2 of the Stratix III Device Handbook for the
programmable output buffer delay specifications.
that can be activated to ensure zero hold times, minimize setup
DC and Switching Characteristics of Stratix III Devices
DC and Switching Characteristics of Stratix III Devices
Figure
7–8. The delay chains can
Altera Corporation
November 2007