EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 204

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–54
Stratix III Device Handbook, Volume 1
scandone
scandataout
Table 6–15. Real-Time PLL Reconfiguration Ports (Part 2 of 2)
PLL Port Name
Indicates when the PLL has
finished reprogramming. A rising
edge indicates the PLL has
begun reprogramming. A falling
edge indicated the PLL has
finished reprogramming.
Used to output the contents of
the scan chain.
The procedure to reconfigure the PLL counters is shown below:
1.
2.
3.
4.
5.
6.
7.
The scanclkena signal is asserted at least one scanclk cycle prior
to shifting in the first bit of scandata (Dn).
Serial data (scandata) is shifted into the scan chain on the 2nd
rising edge of scanclk.
After all 234 bits (Top/Bottom PLLs) or 180 bits (Left/Right PLLs)
have been scanned into the scan chain, the scanclkena signal is
de-asserted to prevent inadvertent shifting of bits in the scan chain.
The configupdate signal is asserted for one scanclk cycle to
update the PLL counters with the contents of the scan chain.
The scandone signal goes high indicating the PLL is being
reconfigured. A falling edge indicates the PLL counters have been
updated with new settings.
Reset the PLL using the areset signal if you make any changes to
the M or N counters or the Icp, R, or C settings.
Steps 1-5 can be repeated to reconfigure the PLL any number of
times.
Description
PLL reconfiguration
circuit
PLL reconfiguration
circuit
Source
Logic array or I/O pins
Logic array or I/O pins
Altera Corporation
Destination
November 2007