EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 65

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
October 2007
Notes to
(1)
(2)
(3)
DSP blocks
Column IOE
Row IOE
Table 3–1. Stratix III Device Routing Scheme (Part 2 of 2)
Source
Except column IOE local interconnects.
Row IOE local interconnects.
Column IOE local interconnects.
Table
3–1:
Shared
Arith-
Chain
metic
—
—
—
Chain
Carry
—
—
—
Regis-
Chain
The R4 and C4 interconnects provide superior and flexible routing
capabilities. Stratix III has a three-sided routing architecture which
allows the interconnect wires from each LAB to reach the adjacent LABs
to its right and left. A given LAB can drive 32 other LABs using one R4 or
C4 interconnect, in one hop. This routing scheme improves efficiency and
flexibility by placing all the critical LABs within one hop of the routing
interconnects.
Table 3–2
hops using the R4 and C4 interconnects.
—
—
—
ter
Table 3–2. Number of LABs reachable using C4 and R4 interconnects
connect
Local
Inter-
—
—
—
shows how many LABs are reachable within one, two, or three
connect
Direct
Inter-
Link
v
—
v
Hops
1
2
3
connect
Inter-
v
—
v
R4
connect
Inter-
R20
v
—
—
Destination
connect
MultiTrack Interconnect in Stratix III Devices
Inter-
v
v
v
C4
connect
Stratix III Device Handbook, Volume 1
Inter-
C12
v
—
—
Number of LABs
ALM
—
—
—
MLAB
Block
160
RAM
—
—
—
34
96
Block
M9K
RAM
—
—
—
M144K
Block
—
—
—
Blocks
DSP
—
—
—
3–7
umn
Col-
IOE
—
—
—
Row
IOE
—
—
—